In many computer applications, various devices need to communicate. Often, these devices operate at different clocking frequencies or at the same frequency but asynchronously. The usual method to synchronize such devices so that they may communicate is to use a synchronizer.
A known synchronizer is shown in FIG. 1 generally at 100. Synchronizer 100 is an N-stage synchronizer. This synchronizer has a number of stages and there is a flip-flop at each stage. The flip-flops at adjacent stages are connected in series. As shown in FIG. 1, synchronizer 100 has first stage flip-flop 102, second stage flip-flop 104, and Nth-stage flip-flop 106. These are representative of all of the N flip-flops of synchronizer 100.
The asynchronous signal input at 108 is input to the data input first stage flip-flop 102. This flip-flop is clocked according to destination time domain clock signal 110. The data input of each of the remaining N-1 flip-flops is loaded by the output from the previous stage flip-flop and each of the remaining N-1 flip-flops is clocked by destination time domain clock signal 110. The result is synchronous output 112.
The greater the number of series-connected flip-flops, the more likely that the output of the synchronizer will not go to a metastable state. Moreover, the greater the number of flip-flops, the more likely that the output of the synchronizer will be fully synchronized. However, a significant drawback of a N-stage synchronizer, such as that shown in FIG. 1, is that the greater the number of stages, the greater the latency from the asynchronous input to the synchronous output. The alternative is to accept the latency, or use of fewer number flip-flop stages and accept reduced reliability.
An example illustrating the latency problem will be explained referring to FIG. 2. A portion of a state machine is shown generally at 200. This state machine is required to generate a synchronous signal in a predetermined time domain when, and if, it reaches State C 214. As is shown, the state machine progresses from State A 210 to State B 212, and then to State C 214 or D 216. Known systems process signals through States A 210 and B 212, and if state machine 200 enters State C 214, the state machine will then synchronize the signal. In this case, the synchronization latency is accepted.
Accordingly, there is a need for a synchronizer that reduces latency problems without reducing reliability. These problems and other problems are addressed by the present invention that is disclosed in the remainder of the specification and shown in the drawings.